Functional Design Verification

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Functional Design Verification

At Suresh Chips & Semiconductors, we provide comprehensive functional design and verification services to ensure your digital systems operate flawlessly. Our experienced team uses advanced methodologies and tools to deliver robust and reliable designs.

“With proven expertise in Verification languages and methodologies such as System Verilog/UVM, we provide high quality verification services ranging from test plan and specification, Coverage Driven Verification and Closure.”


  • Verification planning, feature extraction, capturing functional coverage and check points for SoC/ASIC/Subsystems/IP Functional Verification
  • Architecture support of UVM.
  • Assertion-based verification using SVA.
  • Metric driven verification techniques using advanced tools to increase the verification confidence.
  • Formal verification techniques.
  • Verification IP (VIP) developments.
  • Integration of third-party IP.
  • Creation of wrappers and multi-language interface sockets.
  • Creation of reference models using traditional HDL languages and advanced HVL languages like System Verilog, C++, C.
  • Regression management.
  • FPGA prototyping, emulation platforms and system demonstrators.
  • Low-power verification techniques – power estimation, CPF/UPF.
  • Gate level simulation.
  • Register abstraction-based flow enabling design and verification reuse.
  • Design of always-on agents and protocol checkers.
  • Cycle accurate C modelling of module and complete systems.
  • Use of PLI for co-simulation of embedded processors.
  • End-to-end verification closure from specification to RTL signoff..

Verification Strategy

  • Expertise: We do full SoC/ASIC/Subsystem/IP level verification, using UVM/SystemVerilog, C++ and C.
  • Engagement Models: We offer flexible engagement models, ranging from consulting to full turnkey verification environments.
  • Testbench migration: We can migrate your directed testbenches to methodology based, reusable, coverage driven, constrained random testbench environments with live tracking capabilities.
  • Team Bring Up: We offer planning and configuration set-up that will train your development and management teams on the benefits, savings, and de-risking techniques leveraged in Verification.
  • Verification Planning: In scenarios where we bring specific domain expertise, we can provide the entire planning process. When the domain expertise resides with you, we provide consulting to coordinate your planning effort. In addition, we help you reach your quality goals through feature categorizing and live test-plan creation.
  • Constrained Random Verification (CRV): We offer constrained random verification services to augment your existing environments.
  • Assertion-Based Verification (ABV): We provide Assertion-Based Verification in your existing environment.
  • Directed Testing: For simple FPGA flows, we can offer Directed Testing solutions.
  • RISC-V and Processor Verification: We provide full design verification services for RISC-V and Processor.
  • Verification IP: We can develop verification IPs for standard protocols like PCIe, CXL, DDR, LPDDR, USB, Ethernet, Ethercat, AXI, ATP, ATB, GFB, CXS, LPI