We provide Different certificate courses for Working professionals and Fresh graduate Engineers for Design and Verification.
We provide trainings on :-
- Digital & Verilog HDL
- SystemVerilog HVL
- UVM
- SV Assertion
- Gate Level Simulation
- Low power design
Digital & Verilog HDL
Digital Design Fundamentals
- Basic Fundamentals (Number System, Boolean Algebra, Logic Gates, Logic Optimizations)
- Combinational Logic Design
- Sequential Logic Circuits & Finite State Machines
- Concept & Fundamentals
- Structural Modeling
- Behavioral Modeling
- Building Behavioral Models
Verilog For Verification
- Verilog Operators & Directives
- Verilog Testbench Constructs
- Built-in System Functions & Tasks
- File I/O Operations
- Randomization & Control Functions
Verification Architecture
- Verification Flow and Simulation Process
- Types of Testbench – Architecture and Applications
- Testbench Building Blocks
- Verification Architecture
Scripting & Automation
- Shell scripts & Linux commands
- Perl Scripts
- Makefile
Writing Testbench
- Testbench Architecture
- Testbench Building blocks
- Step-by-step Guidelines
Final Project
Build Verification IP for one or more the standard based interface.
SYSTEMVERILOG
Fundamentals
- SV Introduction
- Data Types
- Operations and Expressions
- Procedural Statements and Control Flow
Extended features
- Inter-process Communication
- Interface
- Program Blocks
OOP Concepts
- OOP Concepts
- Classes
- Randomization and Constraints
Verification Architecture
- SV Testbench Architectures
- Verification Flow and Simulation Process
- Types of Testbench – Architecture and Applications
- Testbench Building Blocks
- Verification Architecture
Writing a Testbench in System Verilog
- Virtual interface
- TB Top
- Generator, Driver, Monitor
- Scoreboard, Config and Package
Functional Coverage and DPI
- Functional Coverage
- DPI
Functional coverage integration
- Signal and Transaction level Functional Coverage
- Integrating Functional Coverage into SV Testbench
Build a Constrained Random Coverage Driven testbench using SystemVerilog for a complex design
UVM Overview
- UVM Evolution
- UVM Structural Pieces and Classes
- Phases, Reporting, Factory and Config_db
- Introduction to Register Abstraction Layer (RAL)
Writing a Simple UVM Testbench
- UVM Classes and Field Macros
- UVM Environment Architecture
- TB Top, Test, Environment, Agent
- Sequencer, Driver, Monitor, Scoreboard
- Sequence and Sequence Item
- Factory Overriding
Functional Coverage Integration
- Signal level Functional Coverage
- Transaction level Functional Coverage
- Integrating Functional Coverage into UVM Testbench
UVC integration
- UVM Verification Component (UVC)
- UVC Integration into Environment
Writing an advanced UVM Testbench I
- Custom register model building
- Virtual Sequence and Virtual Sequencer
RAL Concepts
- RAL introduction
- Register block
- Adapter and predictor
- Register Access Methods
- RAL sequences
Writing an advanced UVM Testbench II
- Interrupt Handling
- RAL integration into UVM Testbench
- RAL methods usage in UVM testbench
Final Project
Build a UVM Testbench for a complex design
SystemVerilog Assertion
- Introduction to SVA
- Immediate and Concurrent Assertions
- Concurrent Assertions: Sequences
- Assertion Coverage
- Assertion Libraries