We are having expertise of RTL Design using Verilog and System Verilog.

  • IP/SoC Design
  • Micro Architecture Development
  • RTL Coding
  • Linting & CDC
  • IP & SoC Integration
  • Synthesis
  • Timing
  • Performance
  • Low Power


Our UVM Verification experts will not only catch mistakes in your designs, they will also make your design better.

Suresh Chips and Semiconductor Private Limited has extensive experience in Digital Design Verification through the planning and implementation of re-usable verification environments, and supports UVM, SystemVerilog, C++, C. We preserve your investment in legacy simulation environments/tools, help you transition to newer methodologies, and build new verification environments to achieve your quality goals.


  • Verification planning, feature extraction, capturing functional coverage and check points.
  • Architecture support of UVM.
  • Assertion-based verification using SVA.
  • Metric driven verification techniques using advanced tools to increase the verification confidence.
  • Formal verification techniques.
  • Verification IP (VIP) developments.
  • Integration of third party IP.
  • Creation of wrappers and multi-language interface sockets.
  • Creation of reference models using traditional HDL languages and advanced HVL languages like System Verilog, C++, C.
  • Regression management.
  • FPGA prototyping, emulation platforms and system demonstrators.
  • Low-power verification techniques – power estimation, CPF/UPF.
  • Gate level simulation.
  • Register abstraction based flow enabling design and verification reuse.
  • Design of always-on agents and protocol checkers.
  • Cycle accurate C modelling of module and complete systems.
  • Use of PLI for co-simulation of embedded processors.
  • End-to-end verification closure from specification to RTL signoff..


  • Expertise: We do full FPGA and ASIC/SoC verification, using UVM, SystemVerilog, and SystemC.
  • Engagement Models: We offer flexible engagement models, ranging from consulting to full turnkey verification environments.
  • Test bench migration: We can migrate your directed test benches to methodology based, reusable, coverage driven, constrained random testbench environments with live tracking capabilities.
  • Team Bring Up: We offer planning and configuration set-up that will train your development and management teams on the benefits, savings, and de-risking techniques leveraged in Verification.
  • Verification Planning: In scenarios where we bring specific domain expertise, we can provide the entire planning process. When the domain expertise resides with you, we provide consulting to coordinate your planning effort. In addition, we help you reach your quality goals through feature categorizing and live test-plan creation.
  • Verification IP: We can develop verification IPs for standard protocols like AMBA, AXI, PCIe, Ethernet, DDR, USB, SATA, SerDes, UART, I2C, DDR, etc.
  • Constrained Random Verification (CRV): We offer constrained random verification services to augment your existing environments.
  • Assertion-Based Verification (ABV): We can train your design and verification teams on Assertion-Based Verification and will bind, track and measure these in your existing environments.
  • Directed Testing: For simple FPGA flows, we can offer Directed Testing solutions.
  • EDA Validation: We provide EDA Validation services for language and performance testing, etc.

Physical Design Expertise

  • Top and block level physical implementation
  • Analog block integration
  • Low Power Methodology
  • Floor planning & Partitioning
  • Physical Synthesis
  • Clock tree Synthesis
  • Place/Route
  • Scan Recording
  • Timing Closure
  • Signal Integrity Analysis
  • Power/EM/IR/Noise
  • Physical Verification
  • Custom Layout

Analog Layout 

  • Block level and full chip layouts
  • Floor planning, Placement, Routing
  • Matching transistor pairs
  • Shielding critical nets
  • EM&IR analysis and repair
  • Expertise in Data Converters, IOs, Clocking Circuits (PLL, DLL), Serdes, Memories, PMUs and RF layouts
  • Process Nodes: 16nm/14nm/10nm/7nm
  • Expertise in Bulk CMOS, SOI and BCD processes


We are developing core processor chips for intelligent cloud servers, intelligent terminals, and intelligent robots.